Processor with execution unit wait control
AssigneeTexas Instruments Deutschland GmbH
InventorsHorst Diewald, Johann Zipperer
Life of this patent
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Abstract
A processor includes a processor core. The processor core includes a first execution unit and a second execution unit. The first execution unit is configured to 1) execute a complex instruction that requires multiple instruction cycles to execute; 2) generate a wait signal that when asserted suspends execution of instructions by the second execution unit for at least a portion of the execution of the complex instruction; and 3) maintain information defining parameters of the wait signal generation across interruption of the complex instruction by execution of a different instruction in the first execution unit.
Claims26
A processor, comprising:
- a processor core, comprising:
- a first execution unit;
- and
- a second execution unit;
- wherein the first execution unit is configured to:
- execute a complex instruction that requires multiple instruction cycles to execute;
- generate a wait signal that when asserted suspends execution of instructions by the second execution unit for at least a portion of the execution of the complex instruction;
- and
- maintain information defining parameters of the wait signal generation across interruption of the complex instruction by execution of a different instruction in the first execution unit.
A processor, comprising:
- a processor core, comprising:
- a plurality of execution units, a first of the execution units is configured to:
- suspend execution of instructions responsive to reception of a first wait signal by the first execution unit;
- and
- execute instructions of a request service while instruction execution is suspended responsive to the first wait signal.
A processor, comprising:
- an execution unit;
- and
- a hardware component external to the execution unit;
- wherein the execution unit is configured to:
- execute a complex instruction that requires multiple instruction cycles to execute;
- generate a wait signal that when asserted suspends operation of the hardware component for at least a portion of the execution of the complex instruction;
- and
- maintain information defining parameters of the wait signal generation across interruption of the complex instruction by execution of a different instruction in the execution unit.
Dependencies are inferred from the claim text.