Memory tile access and selection patterns
AssigneeMicron Technology, Inc.
InventorsHernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
Life of this patent
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Abstract
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
Claims26
An apparatus comprising:
- a plurality of memory tiles including a first memory tile, each memory tile of the plurality of memory tiles comprising an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors;
- and
- selection circuitry including line drivers configured to select a storage component of a memory tile of the plurality of memory tiles based on a corresponding digit line conductor and a corresponding access line conductor to the storage component,
- wherein the selection circuitry is configured to select two or more storage components of the first memory tile in a consecutive manner before selecting the storage components of a different memory tile of the plurality of memory tiles.
An apparatus comprising:
- a controller configured to:
- switch a plurality of switching devices to select a storage component of a plurality of memory tiles according to a memory address associated with at least a digit line conductor and an access line conductor for the storage component, each memory tile of the plurality of memory tiles comprising an array of uniquely addressable storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors, and
- determine a next memory address to select with the plurality of switching devices based at least partly on a previously selected memory address;
- and
- a memory configured to store the next memory address,
- wherein the controller is configured to select two or more storage components of a memory tile of the plurality of memory tiles in a consecutive manner before selecting the storage components of a different memory tile of the plurality of memory tiles.
A method of operating a memory device, the method comprising:
- determining memory addresses of storage locations of a memory tile of a plurality of memory tiles, each of the memory addresses having a corresponding digit line conductor and a corresponding access line conductor, each memory tile of the plurality of memory tiles comprising an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors;
- and
- selecting the corresponding digit line conductors and the corresponding access line conductors to the determined memory addresses of the storage locations of the memory tile to access the storage locations of the memory tile,
- wherein at least two or more storage components of the memory tile are selected before selecting the storage components of a different memory tile of the plurality of memory tiles.
A method to access a memory device, the method comprising:
- determining a memory address of a storage location having a corresponding digit line conductor and a corresponding access line conductor in a memory tile based at least partly on a previously selected memory address in the memory tile;
- and
- selecting the corresponding digit line conductor and the corresponding access line conductor of the determined memory address to access the storage location of the memory tile,
- wherein the corresponding digit line conductor and the corresponding access line conductor of the determined memory address differ from a digit line conductor and from an access line conductor of the previously selected memory address in the memory tile.
Dependencies are inferred from the claim text.