Least-recently-used (lru) to first-dirty-member distance-maintaining cache cleaning scheduler

A cache memory circuit, comprising:

• a plurality of cache line storage locations;
• and
• a control logic that, for each congruence class of the cache memory circuit, determines an indication of a number of line allocations that can be supported by the current state of the congruence class without causing a write-back of a dirty line, compares the indication to a specified clean distance value to determine when to schedule write-backs of dirty lines of the cache memory circuit, and responsive to determining that write-backs should be scheduled, schedules the write-backs of one or more of the dirty lines.

A memory subsystem, comprising:

• a system memory;
• a cache memory hierarchy comprising a plurality of cache memories each comprising a plurality of cache line storage locations, wherein a highest-order one of the cache memories comprises a control logic that, for each congruence class of the highest-order one of the cache memories, determines an indication of a number of line allocations that can be supported by the current state of the congruence class without causing a write-back of a dirty line, compares the indication to a specified clean distance value to determine when to schedule write-backs of dirty lines of the highest-order one of the cache memories, and responsive to determining that write-backs should be scheduled, schedules the write-backs of one or more of the dirty lines.