Data Filter Cache Designs for Enhancing Energy Efficiency and Performance in Computing Systems

A device comprising:

• a level one (L1) data cache;
• a data filter cache, the data filter cache comprising a portion of data stored in the L1 data cache;
• and
• at least one processor, wherein the at least one processor is configured to:
• determine a memory address comprising a calculated tag and index;
• determine a base address tag and index associated with a data filter cache;
• determine whether to perform speculative access of the data filter cache based at least in part on a base address and an offset associated with the memory address;
• when the determination is to perform speculative access, access the data filter cache to obtain data;
• when the determination is to not perform speculative access, access the L1 data cache to obtain the data.

A system comprising:

• at least one memory comprising computer-executable instructions;
• and
• at least one processor configured to execute the computer-executable instructions to:
• access a data filter cache and a level one (L1) data cache, the data filter cache comprising one or more first lines, the one or more first lines having a capacity that is less than a capacity of one or more second lines in the L1 data cache;
• determine, based at least in part on the accessing, that data was missed in the data filter cache;
• after determining that the data was missed in the data filter cache, access the data in the L1 data cache, wherein the accessing comprises the at least one processor being further configured to:
• compare a first tag associated with the data missed from the data filter cache to one or more second tags associated with the one or more second lines in the L1 data cache;
• determine that the first tag matches a second tag of the one or more second tags;
• and
• determine the data in the L1 data cache that corresponds to the first tag;
• and
• store the data from the L1 data cache in the data filter cache.