Multiple transaction data flow control unit for high-speed interconnect

A computer system, comprising:

• a System on a Chip (SoC), including,
• a ring interconnect having a plurality of nodes including a serial interconnect interface node;
• a plurality of processor cores, each operatively coupled to a respective node and including a cache comprising at least one cache level;
• and
• a first serial interconnect link interface, operatively coupled to the serial interconnect interface node and configured to interface with a serial interconnect link comprising a plurality of lanes and implemented using a coherent multi-layer protocol, and further including logic comprising a first agent configured to implement a flow control unit (Flit) employed by the coherent multi-layer protocol having a basic format that supports a plurality of specific formats employing corresponding field configurations including a multiple transaction data format that facilitates transfer of multiple pieces of transaction data relating to a coherent memory transaction in a single Flit.

The system of claim 16, further comprising:

• a memory controller having a second serial interconnect link interface;
• and
• a serial interconnect link having opposing ends coupled to the first serial interconnect link interface and the second serial interconnect link interface,
• wherein the second serial interconnect link interface includes logic comprising a second agent configured to interact with the first agent to facilitate transfer of multiple pieces of transaction data over the serial interconnect link using the single Flit.