Multi master arbitration scheme in a system on chip
AssigneeTexas Instruments Incorporated
InventorSaya Goud Langadi
Life of this patent
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Abstract
A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.
Claims19
A multi-master system on chip, comprising:
- a plurality of masters comprising a first master and a second master, each of the plurality of masters configured to generate a request;
- and
- a next state generator configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer;
- wherein the round robin pointer configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer, and wherein the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.
A method for arbitrating in a multi-master system on chip, the method comprising:
- generating a request from a plurality of masters comprising a first master and a second master;
- generating a next state of a round robin pointer in response to the request and a current state of the round robin pointer;
- and
- generating an enable signal to enable a priority encoder for the first master in response to the next state of the round robin pointer, such that priority for the first master is maintained until there is a request from the second master.
A multi-master system on chip, comprising:
- a plurality of masters comprising a first master and a second master, each of the plurality of masters configured to generate a request;
- a next state generator having a multiplexer configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer;
- and
- a plurality of priority encoders, each associated with the plurality of masters configured to generate a grant signal to the associated master that completes the request;
- wherein:
- the round robin pointer configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer;
- and
- the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.
Dependencies are inferred from the claim text.