Camera control interface extension bus

An apparatus comprising:

• a bus interface adapted to couple the apparatus to a two-wire serial bus operable to be shared with a plurality of other devices;
• and
• a processing circuit coupled to the bus interface, the processing circuit configured to:
• generate a transition number from a set of bits;
• convert the transition number into a 12-symbol sequence of symbols, wherein timing information is encoded in transitions between symbols in the sequence of symbols;
• and
• transmit the sequence of symbols on a two-wire serial bus when the two-wire serial bus is operated in a first mode of operation, wherein each transition between consecutive symbols causes a change in a signaling state of the two-wire serial bus, and
• wherein the sequence of symbols is ignored by a device configured for communicating on the two-wire serial bus when the two-wire serial bus is operated in a second mode of operation.

A method operable on a data communication receiving device and comprising:

• deriving a receive clock from transitions in signaling state of a two-wire serial bus when the two-wire serial bus is operated in a first mode of operation;
• using the receive clock to receive a 12-symbol sequence of symbols that is transmitted on the two-wire serial bus in accordance with the first mode of operation, wherein the transitions in signaling state of the two-wire serial bus correspond to transitions between symbols in the sequence of symbols;
• generating a transition number from the sequence of symbols, wherein the transition number has multiple digits, with each digit representing a transition between a pair of consecutive symbols in the sequence of symbols;
• and
• decoding data from the transition number,
• wherein the sequence of symbols is ignored by a device configured for communicating on the two-wire serial bus when the two-wire serial bus is operated in a second mode of operation.

An apparatus comprising:

• a bus interface adapted to couple the apparatus to a two-wire serial bus operable to be shared with a plurality of other devices;
• a clock recovery circuit configured to derive a receive clock from transitions in signaling state of a two-wire serial bus;
• and
• a processing circuit coupled to the bus interface, the processing circuit configured to:
• use the receive clock to receive a 12-symbol sequence of symbols that is transmitted on the two-wire serial bus in accordance with a first mode of operation, wherein the transitions in signaling state of the two-wire serial bus correspond to transitions between symbols in the sequence of symbols;
• generate a transition number from the sequence of symbols, wherein the transition number has multiple digits, with each digit representing a transition between a pair of consecutive symbols in the sequence of symbols;
• and
• decode data from the transition number,
• wherein the sequence of symbols is ignored by a device configured for communicating on the two-wire serial bus when the two-wire serial bus is operated in a second mode of operation.