Selectively Transparent Bridge for Peripheral Component Interconnect Express Bus Systems

A configuration block for configuring a PCIe (Peripheral Component Interconnect Express) subsystem that comprises PCIe devices coupled to a host system, the configuration block comprising:

• an interface for transmitting and receiving PCIe packets to and from the PCIe subsystem and the host system;
• and
• a processing element configured to:
• create a virtual bus topology corresponding to an actual bus topology of the PCIe subsystem;
• selectively hide a subset of the PCIe devices from the host system by omitting the subset of the PCIe devices from the virtual bus topology, resulting in the subset of the PCIe devices being hidden from the host system, and remaining devices of the PCIe devices being visible to the host system;
• make the virtual bus topology apparent to the host system during configuration of the PCIe devices;
• intercept configuration packets generated by the host system based on the virtual bus topology for configuring the visible remaining devices;
• and
• configure the selectively hidden subset of the PCIe devices and the visible remaining devices according to the actual bus topology, and based at least partially on contents of the intercepted configuration packets.

A method for configuring and operating PCIe (Peripheral Component Interconnect Express) devices comprised in a PCIe subsystem coupled to a host system, the method comprising:

• creating a virtual bus topology corresponding to an actual bus topology of the PCIe subsystem;
• selectively hiding a subset of the PCIe devices from the host system by not including in the virtual bus topology the subset of the PCIe devices, while including in the virtual bus topology remaining ones of the PCIe devices not included in the subset of the PCIe devices;
• making the virtual bus topology apparent to the host system during configuration of the PCIe devices;
• intercepting configuration packets transmitted by the host system to the remaining ones of the PCIe devices;
• and
• configuring the PCIe devices according to the actual bus topology, and based at least partially on contents of the intercepted configuration packets.