Gate driver circuit

A gate driver circuit comprising a plurality of series-coupled shift register stages, an n-th shift register stage of the shift register stages comprising:

• a pull-up unit configured for receiving a first clock signal and an n-th operating signal, wherein when the n-th operating signal is at high logic level, the pull-up unit generates an n-th driving signal according to the first clock signal;
• a pull-up control unit configured for receiving the first clock signal, the n-th operating signal, and the n-th driving signal, wherein when the n-th operating signal is at high logic level, the pull-up control unit outputs the n-th driving signal to an (n+1)-th shift register stage according to the first clock signal;
• and
• an output unit configured for receiving the n-th driving signal, generating a first gate driving signal according to a first controlling signal, and generating a second gate driving signal according to a second controlling signal, wherein the first controlling signal and the second controlling signal are non-overlapped.