Field-effect transistor (fet) with source-drain contact over gate spacer
AssigneeInternational Business Machines Corporation
InventorsKevin K. Chan, Wilfried E. Haensch, Effendi Leobandung, Min Yang
Life of this patent
Estimating the term…
Abstract
A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.
Claims20
A method for constructing a field-effect transistor (FET), the method comprising:
- forming a source region and a drain region in a substrate;
- forming gate spacers over the source region and the drain region, the gate spacers including a gate spacer height;
- epitaxially growing a source contact and a drain contact, the source contact contacting the source region and extending beyond the gate spacer height, the drain contact contacting the drain region and extending beyond the gate spacer height;
- forming an electrically conductive gate above and intermediate to the source region and the drain region;
- and
- wherein the gate is formed after epitaxially growing the source contact and the drain contact.
2-4. (canceled)
(canceled)
A method for constructing a field-effect transistor (FET), the method comprising:
- forming a source region and a drain region in a substrate;
- forming gate spacers over the source region and the drain region, the gate spacers including a gate spacer height;
- epitaxially growing a source contact and a drain contact, the source contact contacting the source region and extending beyond the gate spacer height, the drain contact contacting the drain region and extending beyond the gate spacer height;
- depositing a dielectric layer over the source contact and the drain contact;
- and
- etching the dielectric layer to form vias in the dielectric layer, the vias exposing the source contact and the drain contact;
- depositing a conductive material within the vias;
- and
- annealing the conductive material to form silicide at the top contract area.
A method for constructing a field-effect transistor (FET), the method comprising:
- forming a source region and a drain region in a substrate;
- forming gate spacers over the source region and the drain region, the gate spacers including a gate spacer height;
- epitaxially growing a source contact and a drain contact, the source contact contacting the source region and extending beyond the gate spacer height, the drain contact contacting the drain region and extending beyond the gate spacer height;
- forming an electrically conductive gate above and intermediate to the source region and the drain region;
- depositing a dielectric layer over the conductive gate, the source contact and the drain contact;
- and
- etching the dielectric layer to form vias in the dielectric layer, the vias exposing the source contact and the drain contact;
- depositing a conductive material within the vias;
- and
- annealing the conductive material to form silicide at a top contract area;
- wherein each of the source contact and the drain contact includes a bottom contract area at a first end, the bottom contact area electrically coupled to the source region and the drain region;
- wherein each of the source contact and the drain contact includes the top contract area at a second end opposite the first end;
- and
- wherein the top contract area is greater than the bottom contact area.
11-20. (canceled)
Dependencies are inferred from the claim text.