Semiconductor device and manufacturing method thereof
AssigneeFuji Electric Co., Ltd.
InventorsYoshiaki TOYODA, Akio KITAMURA
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AssigneeFuji Electric Co., Ltd.
InventorsYoshiaki TOYODA, Akio KITAMURA
Estimating the term…
A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an n− semiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer (3) of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.
1-6. (canceled)
A method of manufacturing a semiconductor device having a first region in which a vertical semiconductor element is disposed and a second region in which a lateral semiconductor element electrically isolated from the vertical semiconductor element by an isolating structure is disposed, the semiconductor device manufacturing method comprising:
A method of manufacturing a semiconductor device having a first region in which a vertical semiconductor element is disposed and a second region in which a lateral semiconductor element electrically isolated from the vertical semiconductor element by an isolating structure is disposed, the semiconductor device manufacturing method comprising:
A method of manufacturing a semiconductor device having a first region in which a vertical semiconductor element is disposed and a second region in which a lateral semiconductor element electrically isolated from the vertical semiconductor element by an isolating structure is disposed, the semiconductor device manufacturing method comprising:
A method of manufacturing a semiconductor device having a first region in which a vertical semiconductor element is disposed and a second region in which a lateral semiconductor element electrically isolated from the vertical semiconductor element by an isolating structure is disposed, the semiconductor device manufacturing method comprising:
A method of manufacturing a semiconductor device having a first region in which a vertical semiconductor element is disposed and a second region in which a lateral semiconductor element electrically isolated from the vertical semiconductor element by an isolating structure is disposed, the semiconductor device manufacturing method comprising:
Dependencies are inferred from the claim text.