Back to results
US 2014/0370667 A1Published application
Tapered nanowire structure with reduced off current
AssigneeInternational Business Machines Corporation
InventorsJeffrey W. Sleight, Sarunya Bangsaruntip
Life of this patent
Estimating the term…
Abstract
Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.
Claims19
A method of forming a non-planar semiconductor device comprising:
- forming at least one semiconductor nanowire above an insulator layer of a semiconductor-on-insulator substrate, wherein an end segment of said at least one semiconductor nanowire is attached to a first semiconductor-on-insulator pad region and another end segment of said at least one semiconductor nanowire is attached to a second semiconductor-on-insulator pad region, said pad regions are both located atop said insulator layer;
- forming at least one semiconductor nanowire into at least one tapered semiconductor nanowire comprising a first semiconductor nanowire portion having a first width, a second semiconductor nanowire portion having a second width and a third semiconductor nanowire portion having a third width, wherein said third semiconductor nanowire portion is located between the first and second semiconductor nanowire portions, and said first width is less than the third width, and wherein said third width is less than the second width;
- forming a gate atop said third semiconductor nanowire portion of said at least one semiconductor nanowire, wherein said first semiconductor nanowire portion is located on a first side of the gate and said second semiconductor nanowire portion is located on a second side of the gate that is opposite to said first side;
- and
- forming a source region on said first side of the gate and forming a drain region of the second side of the gate.
2 more elements
A method of forming a non-planar semiconductor device comprising:
- forming at least one tapered semiconductor nanowire above an insulator layer of a semiconductor-on-insulator substrate, wherein an end segment of said at least one tapered semiconductor nanowire is attached to a first semiconductor-on-insulator pad region and another end segment of said at least one tapered semiconductor nanowire is attached to a second semiconductor-on-insulator pad region, said pad regions are both located atop said insulator layer, and wherein said at least one tapered semiconductor nanowire comprises a first semiconductor nanowire portion having a first width, a second semiconductor nanowire portion having a second width and a third semiconductor nanowire portion having a third width, wherein said third semiconductor nanowire portion is located between the first and second semiconductor nanowire portions, and wherein said first width is less than the third width, and said third width is less than the second width;
- forming a gate atop said third semiconductor nanowire portion of said at least one tapered semiconductor nanowire, wherein said first semiconductor nanowire portion is located on a first side of the gate and said second semiconductor nanowire portion is located on a second side of the gate that is opposite to said first side;
- and
- forming a source region on said first side of the gate and forming a drain region of the second side of the gate.
1 more element
Dependencies are inferred from the claim text.