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US 2014/0369453 A1Published application
Receivers and semiconductor systems including the same
AssigneeSK hynix Inc.
InventorKeun Soo SONG
Life of this patent
Estimating the term…
Abstract
The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data.
Claims25
A semiconductor system comprising:
- a transmitter configured to generate a data strobe signal and a data;
- and
- a receiver configured to generate an internal clock signal in response to the data strobe signal, configured to retard the internal clock signal to generate a delayed internal clock signal, and configured to buffer the data in response to the delayed internal clock signal to generate an input data.
A receiver comprising:
- a first buffer configured to buffer a data in synchronization with a first internal clock signal to generate a first internal data;
- a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal;
- and
- a second buffer configured to buffer the first internal data in synchronization with the first delayed internal clock signal to generate a first input data.
1 more element
A semiconductor system comprising:
- a transmitter configured to generate a first internal clock signal, a second internal clock signal, and a data;
- and
- a receiver configured to retard the first and second internal clock signals to generate a first delayed internal clock signal and a second delayed internal clock signal, configured to buffer the data in synchronization with the first and second internal clock signals, and configured to buffer the buffered data in synchronization with the first and second delayed internal clock signals to generate a first input data and a second input data.
A receiver comprising:
- a first buffer configured to amplify a data to output the data as a first internal data;
- a first delay unit configured to include an inverter chain to retard a first internal clock signal;
- and
- a second buffer configured to buffer the first internal data to generate a first input data.
1 more element
Dependencies are inferred from the claim text.