Low Power Oversampling With Reduced-Architecture Delay Locked Loop
AssigneeIntel Corporation
InventorWei-Lien Yang
Life of this patent
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Abstract
In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.
Claims20
A mobile system comprising:
- a radio frequency (RF) transceiver to communicate wirelessly via an antenna;
- a baseband processor coupled to the RF transceiver, the baseband processor including at least one core and a receiver logic, the receiver logic comprising:
- a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal;
- a controller unit to generate a delay signal based on the phase difference;
- and
- a set of voltage-controlled delay buffers to generate a plurality of phase outputs based on the delay signal, the plurality of phase outputs provided to a clock generator unit to generate an oversampled clock signal for data recovery;
- and
- a touchscreen display coupled to the baseband processor.
A system comprising:
- a multicore processor including a plurality of cores and a receiver logic, the receiver logic comprising:
- a digital delay-locked loop circuit to:
- receive and invert a reference pulse-width modulated (PWM) clock signal and a gear selection input;
- determine a phase difference between the inverted reference PWM clock signal and a feedback clock signal;
- and
- generate a plurality of phase output signals based on the phase difference;
- and
- a clock generator device to generate an oversampled clock signal based on the plurality of phase output signals, the oversampled clock signal to be used for data recovery by the receiver logic;
- and
- a disk drive coupled to the multicore processor configured to store code to execute on the multicore processor;
- and
- wherein the system does not include a radio hardware configured for wireless voice communication.
A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- determining a phase difference between an inverted reference clock signal and a feedback clock signal;
- generating a delay signal based on the phase difference;
- generating a plurality of phase outputs using a delay-locked loop circuit;
- and
- generating an oversampled clock signal based on the plurality of phase outputs, the oversampled clock signal for use in performing data recovery by a receiver.
Dependencies are inferred from the claim text.