US 2014/0369152 A1Published application

N-well switching circuit

AssigneeQUALCOMM Incorporated

InventorsEsin Terzioglu, Gregory Ameriada Uvieghara, Sei Seung Yoon, Balachander Ganesan, Anil Chowdary Kota

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Abstract

A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Claims16

Dependent claims

A circuit, comprising:

a thin-oxide PMOS transistor having a source and a switched n-well;
a native thick-oxide NMOS transistor having a gate controlled responsive to a control signal, a drain coupled to a low-voltage supply configured to provide a low voltage, and a source coupled to the thin-oxide PMOS transistor's source and switched n-well;
and
a thick-oxide PMOS transistor having a gate controlled responsive to the control signal, a source coupled to a high-voltage supply configured to provide a high voltage that is greater than the low voltage, and a drain coupled to the thin-oxide PMOS transistor's source and switched n-well, wherein the native thick-oxide NMOS transistor and the thick-oxide PMOS transistor each have a first gate-oxide thickness that is greater than a second gate-oxide thickness for the thin-oxide PMOS transistor.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 14/472,953Filed 29 Aug 2014
Priority: 16 Jan 2013
Published: 18 Dec 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H03K 17/223
Modifications for ensuring a predetermined initial state when the supply voltage has been applied: in field-effect transistor switches
G11C 7/00
Arrangements for writing information into, or reading information out from, a digital
G11C 7/12
Arrangements for writing information into, or reading information out from, a digital store: bit line control circuits, e.g. drivers, boosters,…
G11C 8/08
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…

Family

Application13/742,964Continuation · filed 16 Jan 2013
Application14/472,953Continuation
US 2014/0198588 A1Published application
US 8,787,096 B1Related patent
US 9,252,765 B2Related patent
US 2014/0369152 A1This patent

From the US filing history. Foreign family members aren’t listed.