High voltage switching circuitry for a cross-point array

A computer-readable medium storing a representation of a circuit component comprising:

• logic including Metal Oxide Semiconductor (MOS) devices and being configured to determine a data operation and activate either a negative voltage level shifter or a positive voltage level shifter as a function of the data operation;
• and
• a driver including other MOS devices and being electrically coupled with the negative voltage level shifter and the positive voltage level shifter, the driver being configured to drive either a negative range of voltages or a positive range of voltages on one or more of a plurality of conductive array lines of a layer of a third dimensional memory;
• wherein the MOS devices and the other MOS devices are configured to operate at or below a first potential difference, and wherein the first potential difference is less than a second potential difference that is associated with modifying a conductivity profile of a re-writeable memory cell having a first terminal couponed to a first conductive array line of the plurality and a second terminal coupled to a second conductive array line of the plurality.

A computer-implemented method for generating a representation of a circuit component, the representation stored on a computer-readable medium, the method comprising:

• including, into the representation using a processing system, logic including Metal Oxide Semiconductor (MOS) devices and being configured to determine a data operation and activate either a negative voltage level shifter or a positive voltage level shifter as a function of the data operation;
• and
• including, into the representation using the processing system, a driver including other MOS devices and being electrically coupled with the negative voltage level shifter and the positive voltage level shifter, the driver being configured to drive either a negative range of voltages or a positive range of voltages on one or more of a plurality of conductive array lines of a layer of a third dimensional memory;
• wherein the MOS devices and the other MOS devices are configured to operate at or below a first potential difference, and wherein the first potential difference is less than a second potential difference that is associated with modifying a conductivity profile of a re-writeable memory cell having a first terminal couponed to a first conductive array line of the plurality and a second terminal coupled to a second conductive array line of the plurality.

An integrated circuit, comprising:

• a substrate;
• a base layer formed on the substrate and including discrete devices configured to operate within a first voltage range;
• a layer of memory formed above the base layer and electrically coupled with the devices in the base layer, the layer of memory including:
• a plurality of conductive array lines;
• and
• a plurality of re-writable memory cells configured to operate within a second voltage range that is greater than the first voltage range, each memory cell including two terminals, configured to modify a conductivity profile of the memory cell in response to a first potential difference applied across the two terminals, and having one terminal electrically coupled with one of the plurality of conductive array lines;
• a first decoder including a first subset of the discrete devices that operate in the first voltage range;
• and
• a second decoder including a second subset of the discrete devices that operate in the first voltage range:
• wherein the first decoder and the second decoder are configured to collectively generate a voltage in the second voltage range but not in the first voltage range and to apply the voltage across the two terminals of at least one of the memory cells, whereby no single discrete device is subject to the second voltage range.