Chip tester and test method of semiconductor device

A chip tester for testing a semiconductor memory device, the semiconductor memory device including guarantee blocks, normal blocks, redundancy blocks, and a meta block in which repair information required to allocate the redundancy blocks for at least one first defective block generated in the normal blocks, the chip tester comprising:

• a test unit suitable for performing a test on the guarantee blocks and for detecting at least one second defective block from the guarantee blocks;
• a storage unit suitable for storing the repair information;
• a determination unit suitable for comparing the number of available redundancy blocks, which are not allocated for the first defective blocks, with the number of the second defective block, by referring to the repair information;
• and
• a guarantee block management unit suitable for updating the repair information to cancel allocation of at least one of the redundancy blocks based on the comparison result.