Data transfer device, buffering circuit, and buffering method
AssigneeFujitsu Limited
InventorYoshihiro Kitahara
Life of this patent
Estimating the term…
Abstract
A data transfer device 2 has a first bank 31 which has a first bank first memory 311 and a first bank second memory 312, a second bank 32 which has a second bank first memory 321 and a second bank second memory 322, and a control circuit. Write and read operations of both the first bank 31 and second bank 32 are performed in the reference period, and alternately changes to the write state and to the read state in the phase opposite to each other. The control circuit 70 controls the first bank 31 and the second bank 32 so that input data groups are stored sequentially in the first bank 31 and in the second bank 32 and the stored data groups are read sequentially.
Claims10
A data transfer device for sequentially writing and storing data groups and reading and outputting the data groups in the order of storage, the data transfer device comprising:
- a first bank having a first bank first memory and a first bank second memory to and from which write and read operations are performed in a reference period, the first bank alternately changing to a write state and to a read state in each of the reference periods;
- a second bank having a second bank first memory and a second bank second memory to and from which write and read operations are performed in the reference period, the second bank alternately changing to a write state and to a read state in a phase opposite to that of the first bank;
- and
- a control circuit configured to perform control so that data groups that are input are sequentially stored in the first bank and in the second bank and the stored data groups are read sequentially.
A buffering circuit comprising:
- a first bank having a first bank first memory and a first bank second memory to and from which write and read are performed in a reference period, the first bank alternately changing to a write state and to a read state in each of the reference periods;
- a second bank having a second bank first memory and a second bank second memory to and from which write and read operations are performed in the reference period, the second bank alternately changing to a write state and to a read state in a phase opposite to that of the first bank;
- and
- a control circuit configured to perform control so that data groups that are input are sequentially stored in the first bank and in the second bank and the stored data groups are read sequentially.
A buffering method using a buffering circuit having:
- a first bank having a first bank first memory and a first bank second memory to and from which write and read operations are performed in a reference period, the first bank alternately changing to a write state and to a read state in each of the reference periods;
- a second bank having a second bank first memory and a second bank second memory to and from which write and read operations are performed in the reference period, the second bank alternately changing to a write state and to a read state in a phase opposite to that of the first bank;
- and
- a control circuit configured to perform control so that data groups that are input are sequentially stored in the first bank and in the second bank and the stored data groups are read sequentially, the buffering method comprising:
- alternately outputting a first bank write enable signal to enable write to the first bank and a second bank write enable signal to enable write to the second bank in each one cycle of the reference period;
- determining which of the first bank and the second bank is in the write enable state, based on the first bank write enable signal and the second bank write enable signal when receiving the first data of the data group;
- writing the first data to the first bank first memory when the first bank is in the write enable state and the first data is allocated to higher-order data;
- writing the first data to the first bank second memory when the first bank is in the write enable state and the first data is allocated to lower-order data;
- writing the first data to the second bank first memory when the second bank is in the write enable state and the first data is allocated to higher-order data;
- writing the first data to the second bank second memory when the second bank is in the write enable state and the first data is allocated to lower-order data,
- storing the bank and the memory to which the first data is written, respectively, and
- incrementing the write address after writing the last data of the data group and setting the next address of the address in which the last data of the data group is written as a write start address of the next data group.
Dependencies are inferred from the claim text.