Semiconductor memory device, memory system including the same, and operating method thereof
AssigneeSK hynix Inc.
InventorWon Hee LEE
Life of this patent
Estimating the term…
Abstract
Disclosed are a semiconductor memory device, a memory system including the same, and an operation method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; and a plurality of page buffers configured to supply currents to bit lines when a sensing operation is performed and sense currents of the bit lines to sense data of the plurality of memory cells and generate current paths between the bit lines and a ground according to program states of the plurality of memory cells.
Claims20
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory cells;
- and
- a plurality of page buffers configured to supply currents to bit lines when a sensing operation is performed, sense currents of the bit lines to sense data of the plurality of memory cells, and generate current paths between the bit lines and a ground according to program states of the plurality of memory cells.
A memory system, comprising:
- a semiconductor memory device including a plurality of memory cells, and a plurality of page buffers;
- and
- a controller configured to control the semiconductor memory device,
- wherein the semiconductor memory device forms a current path connecting bit lines and a ground voltage through the plurality of page buffers according to program states of selected memory cells when a sensing operation is performed in response to a request for a read operation or a verification operation.
A method of operating a semiconductor memory device, comprising:
- supplying a current to a bit line;
- applying a read voltage or a verification voltage to a selected memory cell;
- turning on or turning off the selected memory cell according to a program state so that the current supplied flows to a common source line or is blocked;
- forming an additional current path connecting the bit line and the ground voltage to decrease a potential of the bit line when the current flows to the common source line;
- and
- sensing a state of the selected memory cell according to a potential of the bit line.
Dependencies are inferred from the claim text.