Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTokumasa HARA, Naoya Tokiwa, Hiroshi Sukegawa, Hitoshi Iwai, Toshifumi Shano, Shirou Fujita
Life of this patent
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Abstract
According to one embodiment, a semiconductor memory device includes a first string; a second string; and a controller. The first string is coupled with a first bit line and includes first memory cells. The second string is coupled with a second bit line and includes second memory cells. The controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously. The controller reads data from the first and second strings after writing the first and second data.
Claims19
A semiconductor memory device comprising:
- a first string which is coupled with a first bit line, the first string including first memory cells coupled between a first selection transistor and a second selection transistor in series;
- a second string which is coupled with a second bit line and is adjacent to the first string, the second string including second memory cells coupled between a third selection transistor and a fourth selection transistor in series, wherein gates of the first and third selection transistors are coupled in common and gates of the second and fourth selection transistors are coupled in common;
- and
- a controller which controls access to the memory cells,
- wherein the controller executes writing first data into the first memory cells and writing second data into the second memory cells simultaneously, and
- the controller reads data from the first and second strings after writing the first and second data.
A semiconductor memory device comprising:
- a first string which is coupled with a first bit line, the first string including first memory cells coupled between a first selection transistor and a second selection transistor in series;
- a second string which is coupled with a second bit line and is adjacent to the first string, the second string including second memory cells coupled between a third selection transistor and a fourth selection transistor in series, wherein gates of the first and third transistors are coupled in common and gates of the second and fourth transistors are coupled in common;
- and
- a controller which controls access to the memory cells,
- wherein the controller turns on the first selection transistor and the third selection transistor, turns off the second section transistor and the fourth selection transistor, supplies a first voltage to the first bit line, and supplies a second voltage to the second bit line to read data from the first string.
A semiconductor memory device comprising:
- a first string including first memory cells;
- and
- a controller which controls access to the memory cells,
- wherein the first string includes:
- a first selection transistor;
- a second selection transistor;
- the first memory cells coupled between the first selection transistor and the second selection transistor in series;
- and
- a back-gate transistor provided between a first one of the first memory cells and a second one of the first memory cells,
- wherein the controller reads data from the first string while turning off the back-gate transistor and applying a first voltage to gates of all the first memory cells in the first string.
Dependencies are inferred from the claim text.