Semiconductor Memory Device And Method For Driving The Same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorYasuhiko Takemura
Life of this patent
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Abstract
In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m—1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.
Claims26
A semiconductor memory device comprising:
- a bit line;
- four word lines;
- and
- two cells each including two memory cells, a sub bit line, a first selection transistor, a second selection transistor, and an amplifier circuit,
- wherein a drain of the first selection transistor is connected to the bit line,
- wherein a source of the first selection transistor and a first terminal of the amplifier circuit are connected to the sub bit line,
- wherein a second terminal of the amplifier circuit is connected to a source of the second selection transistor,
- wherein a drain of the second selection transistor is connected to the bit line,
- wherein each of the two memory cells includes a transistor and a capacitor,
- wherein capacitance of the capacitor is 1 fF or less, and
- wherein the transistor of each of the two memory cells comprises a gate connected to one of the four word lines, a drain connected to the sub bit line, and a source connected to one electrode of the capacitor.
A semiconductor memory device comprising:
- a bit line;
- four word lines;
- and
- two cells each including two memory cells, a sub bit line, a first selection transistor, a second selection transistor, and an amplifier circuit,
- wherein a drain of the first selection transistor is connected to the bit line,
- wherein a source of the first selection transistor and a first terminal of the amplifier circuit are connected to the sub bit line,
- wherein a second terminal of the amplifier circuit is connected to a source of the second selection transistor,
- wherein a third terminal of the amplifier circuit is connected to the bit line,
- wherein each of the two memory cells includes a transistor and a capacitor,
- wherein capacitance of the capacitor is 1 fF or less, and
- wherein the transistor of each of the two memory cells comprises a gate connected to one of the four word lines, a drain connected to the sub bit line, and a source connected to one electrode of the capacitor.
A semiconductor memory device comprising:
- a first bit line and a second bit line;
- four word lines;
- and
- a first sub bit line and a second sub bit line,
- wherein two memory cells, a source of a first selection transistor, and a first terminal of an amplifier circuit are connected to the first sub bit line,
- wherein a drain of the first selection transistor is connected to the first bit line,
- wherein a second terminal of the amplifier circuit is connected to a drain of a second selection transistor,
- wherein a third terminal of the amplifier circuit is connected to the second bit line,
- wherein each of the two memory cells includes a transistor and a capacitor,
- wherein capacitance of the capacitor is 1 fF or less, and
- wherein the transistor of each of the two memory cells comprises a gate connected to one of the four word lines, a drain connected to the first sub bit line, and a source connected to one electrode of the capacitor.
A semiconductor memory device comprising:
- a first bit line and a second bit line;
- four word lines;
- a first selection line parallel to the four word lines;
- a second selection line parallel to the four word lines;
- and
- a first sub bit line and a second sub bit line,
- wherein two memory cells, a source of a first selection transistor, and a first terminal of an amplifier circuit are connected to the first sub bit line,
- wherein a gate of the first selection transistor and a gate of a second selection transistor are connected to the first selection line and the second selection line, respectively,
- wherein a drain of the first selection transistor is connected to the first bit line,
- wherein a second terminal of the amplifier circuit is connected to a drain of the second selection transistor,
- wherein a third terminal of the amplifier circuit is connected to the second bit line,
- wherein each of the two memory cells includes a transistor and a capacitor,
- wherein capacitance of the capacitor is 1 fF or less, and
- wherein the transistor of each of the two memory cells comprises a gate connected to one of the four word lines.
Dependencies are inferred from the claim text.