Memory device

A memory device comprising:

• a plurality of global bit lines extending along a first direction;
• a pair of word lines separated from each other, extending along a second direction;
• a first bit line between the pair of word lines, extending along a third direction different from the first direction and the second direction;
• first variable resistivity layers between the first bit line and each word line of the pair of word lines;
• and
• a first selector between the first bit line and one of the plurality of global bit lines,
• wherein the first selector includes:
• a first semiconductor layer coupled with the first bit line and the one of the plurality of global bit lines, and
• a pair of gates on two side surfaces of the first semiconductor layer facing each other in the first direction with first gate insulating layers therebetween.

A memory device comprising:

• a plurality of global bit lines extending along a first direction;
• a pair of word lines extending along a second direction, and separated from each other;
• a first bit line between the pair of word lines, extending along a third direction different from the first direction and the second direction;
• a pair of gates separated from each other in parallel in the first direction, and separated from the pair of word lines in the third direction;
• first variable resistivity layers between the first bit line and each word line of the pair of word lines;
• and
• a pair of gate insulating layers between the first bit line and the pair of gates,
• wherein the first bit line includes a first semiconductor layer coupled with the gate insulating layers in a part thereof, the first semiconductor layer also being coupled with one of the plurality of global bit lines.

A memory device comprising:

• a plurality of global bit lines, each global bit line of the plurality being provided along a first direction;
• a plurality of word lines, each word line of the plurality being provided along a second direction;
• a plurality of bit lines, each bit line of the plurality being provided along a third direction different from the first and second directions;
• a plurality of memory cells including variable resistance layers facing each other on two side surfaces of the bit lines and coupled with mutually different word lines of the plurality of word lines;
• and
• a plurality of selectors, which couple the plurality of bit lines with the plurality of global bit lines,
• wherein one of the plurality of selectors includes a semiconductor layer between associated one of the plurality of bit lines and associated one of the plurality of global bit lines, and
• a plurality of gates on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.