US 2014/0369103 A1Published application

Content addressable memory cells and ternary content addressable memory cells

AssigneeMediatek Inc.

InventorShu-Hsuan Lin

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Abstract

An embodiment of the invention provides a binary CAM cell. The binary CAM cell includes a storage circuit, a first discharging circuit, and a second discharging circuit. The storage circuit is configured to provide a first stored bit and a second stored bit, which are complimentary bits of each other. The first discharging circuit is configured to either discharge or not discharge a match line according to the first stored bit provided by the storage circuit and a first searched bit provided by a first search line. The first discharging circuit includes a first PMOS transistor. The second discharging circuit is configured to either discharge or not discharge the match line according to the second stored bit provided by the storage circuit and a second searched bit provided by a second search line. The second discharging circuit includes a second PMOS transistor.

Claims20

Dependent claims

A TCAM cell, comprising:

a first storage circuit configured to provide a first stored bit;
a first discharging circuit, coupled to the first storage circuit, a first search line, and a match line, configured to either discharge or not discharge the match line according to the first stored bit provided by the first storage circuit and a first searched bit provided by the first search line, the first discharging circuit comprising:
a first PMOS transistor, having a gate coupled to receive one of the first stored bit and the first searched bit;
a second storage circuit configured to provide a second stored bit;
and
a second discharging circuit, coupled to the second storage circuit, a second search line, and the match line, configured to either discharge or not discharge the match line according to the second stored bit provided by the second storage circuit and a second searched bit provided by the second search line, the second discharging circuit comprising:
a second PMOS transistor, having a gate coupled to receive one of the second stored bit and the second searched bit.

4 more elements

A binary CAM cell, comprising:

a storage circuit configured to provide a first stored bit and a second stored bit, wherein the second stored bit is a complimentary bit of the first stored bit;
a first discharging circuit, coupled to the storage circuit, a first search line, and a match line, configured to either discharge or not discharge the match line according to the first stored bit provided by the storage circuit and a first searched bit provided by the first search line, the first discharging circuit comprising:
a first PMOS transistor, having a gate coupled to receive one of the first stored bit and the first searched bit;
and
a second discharging circuit, coupled to the storage circuit, a second search line, and the match line, configured to either discharge or not discharge the match line according to the second stored bit provided by the storage circuit and a second searched bit provided by the second search line, the second discharging circuit comprising:
a second PMOS transistor, having a gate coupled to receive one of the second stored bit and the second searched bit.

3 more elements

Dependencies are inferred from the claim text.