Over-voltage tolerant circuit and method

A circuit comprising:

• a sensing circuit coupled to an I/O pad of an electronic device and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad);
• a latch coupled to the sensing circuit and configured to retain an output of the sensing circuit;
• and
• a pull-down driver coupled between the I/O pad and a circuit ground, the pull-down driver configured to receive a gate hot-swap (pghs_h) signal from the sensing circuit through the latch and to reduce I/O pad leakage,
• wherein the pull-down driver comprises a plurality of legs of increasing pull-down capability coupled in parallel between the I/O pad and the circuit ground, each leg comprising a N-type MOS (NMOS) pull-down transistor, including at least one weak leg having a resistance in series with the NMOS pull-down transistor to implement slew-rate control.

A method comprising:

• applying a first gate signal (P1g) from a non-overlap circuit to a gate of a first select transistor (P1) to couple a supply voltage (Vcc) to a gate and an N-well of a PMOS pull-up transistor coupled to an I/O pad of an electronic device;
• sensing with a sensing circuit a voltage applied to the I/O pad (Vpad) is greater than Vcc+a threshold voltage of the PMOS pull-up transistor (Vtp);
• removing the first gate signal (P1g) from the gate of the first select transistor (P1) and applying a second gate signal (P2g) to a second select transistor (P2) to couple Vpad to the gate and N-well of the PMOS pull-up transistor;
• sensing with the sensing circuit that Vpad is less than Vcc−Vtp;
• and
• removing the second gate signal (P2g) from the gate of the second select transistor (P2) and applying the first gate signal (P1g) from the non-overlap circuit to the first select transistor (P1) to couple Vcc to the gate and N-well of the PMOS pull-up transistor.