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US 2014/0368368 A1Published application
Continuous-Time Mash Sigma-Delta Analogue to Digital Conversion
AssigneeST-Ericsson SA
InventorKimmo Koli
Life of this patent
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Abstract
Continuous-time MASH sigma-delta ADC with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.
Claims16
An analogue-to-digital converter, ADC, comprising:
- a first continuous-time, CT, delta-sigma, ΔΣ, modulator comprising a first analogue stage arranged to generate a first error signal dependent on an input signal, a first feedback signal and a second feedback signal, a first quantiser arranged to generate a first quantised signal by quantising the first error signal into at least three levels at a first sample rate, and a first digital-to-analogue converter, DAC, arranged to generate the first feedback signal from the first quantised signal;
- a second, first order CT ΔΣ modulator comprising a second analogue stage arranged to generate a second error signal dependent on the first error signal, the first feedback signal and the second feedback signal, a second quantiser arranged to generate a second quantised signal by quantising the second error signal into two levels at a second sample rate, and a second DAC arranged to generate the second feedback signal from the second quantised signal;
- and
- an output stage arranged to generate an output signal by summing the first quantised signal and the second quantised signal.
1 more element
A method of analogue-to-digital conversion, comprising:
- in a first continuous-time, CT, delta-sigma, ΔΣ, modulator:
- generating a first error signal dependent on an input signal, a first analogue feedback signal and a second analogue feedback signal,
- generating a first quantised signal by quantising the first error signal into at least three levels at a first sample rate, and
- generating the first analogue feedback signal from the first quantised signal;
- in a second, first order CT ΔΣ modulator:
- generating a second error signal dependent on the first error signal, the first analogue feedback signal and the second analogue feedback signal,
- generating a second quantised signal by quantising the second error signal into two levels at a second sample rate, and
- generating the second analogue feedback signal from the second quantised signal;
- and
- generating an output signal by summing the first quantised signal and the second quantised signal.
7 more elements
Dependencies are inferred from the claim text.