Delay control circuit
AssigneeSK hynix Inc.
InventorKwang Su LEE
Life of this patent
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Abstract
The present invention relates to a delay control circuit and technology in which the amount of delay can be regularly maintained although Process, Voltage, and Temperature (PVT) conditions are changed. The delay control circuit of the present invention includes a ZQ calibration unit configured to generate an impedance code into which a change of PVT conditions has been incorporated, a voltage trimming unit configured to control a level of a trimming voltage at a calibration node, and a delay compensation unit configured to compensate for the amount of delay by controlling an effective capacitance value of a capacitor.
Claims20
A delay control circuit, comprising:
- a ZQ calibration unit configured to generate an impedance code into which a change of Process, Voltage, and Temperature (PVT) conditions has been incorporated;
- a voltage trimming unit configured to control a level of a trimming voltage at a calibration node in response to the impedance code;
- and
- a delay compensation unit configured to compensate for an amount of delay by controlling an effective capacitance value of a capacitor in response to the trimming voltage,
- wherein the ZQ calibration unit comprises a reference voltage generator configured to generate a first reference voltage and a second reference voltage in response to the impedance code, and
- wherein the ZQ calibration unit controls the impedance code by previously change levels of the first reference voltage and the second reference voltage in response to specifications of a device.
A delay control circuit, comprising:
- a ZQ calibration unit configured to generate an impedance code to maintain an impedance value at a target value;
- a voltage trimming unit configured to output a trimming voltage to a delay compensation unit;
- and
- the delay compensation unit configured to configured to output an output clock by compensating a delay of an input clock,
- wherein the ZQ calibration unit comprises a reference voltage generator configured to generate a first reference voltage and a second reference voltage in which a difference between levels of the first reference voltage and the second reference voltage are controlled in response to the impedance code, and
- wherein the ZQ calibration unit controls the impedance code by previously change levels of a reference voltage in response to specifications of a device.
(canceled)
Dependencies are inferred from the claim text.