Clock control device
AssigneeSK hynix Inc.
InventorBok Rim KO
Life of this patent
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Abstract
A clock control device is disclosed, which relates to a technology for reducing the amount of current consumption when a semiconductor device operates at a high speed. The clock control device includes: a chip-select-signal control block configured to generate a chip-select-control signal by latching a chip select signal, and output a fast chip select signal according to the chip-select-control signal; and a clock control block configured to drive a clock signal in response to the fast chip select signal when a command clock enable signal is activated, thereby generating a clock control signal, wherein the chip-select-signal control block latches the chip-select-control signal, and controls the chip-select-control signal to be toggled after the command clock enable signal is transitioned.
Claims20
A clock control device comprising:
- a chip-select-signal control block configured to generate a chip-select-control signal by latching a chip select signal, and output a fast chip select signal according to the chip-select-control signal;
- and
- a clock control block configured to drive a clock signal in response to the fast chip select signal when a command clock enable signal is activated, thereby generating a clock control signal,
- wherein the chip-select-signal control block latches the chip-select-control signal, and controls the chip-select-control signal to be toggled after the command clock enable signal is transitioned.
A clock control device comprising:
- a first buffer configured to buffer a chip select signal during normal operation;
- a second buffer configured to buffer the chip select signal during high-speed operation;
- a chip-select-signal controller configured to generate a fast chip select signal by combining an output signal of the second buffer and a chip-select-control signal;
- a delay unit configured to delay an output signal of the first buffer;
- a latch unit configured to latch an output signal of the delay unit in response to a clock control signal, and output the chip-select-control signal;
- and
- a clock controller configured to control a clock enable signal according to a command clock enable signal, the fast chip select signal, and the clock control signal.
Dependencies are inferred from the claim text.