Back to results
US 2014/0368178 A1Published application
Voltage regulator
AssigneeSeiko Instruments Inc.
InventorOsamu UEHARA
Life of this patent
Estimating the term…
Abstract
Provided is a voltage regulator that uses an NMOS transistor as an output transistor and is low in power consumption. The voltage regulator includes an output transistor formed of an NMOS transistor, and a voltage drop circuit connected between a drain of the output transistor and a power supply.
Claims4
A voltage regulator, comprising:
- an output transistor comprising an NMOS transistor connected between a power supply terminal and an output terminal;
- an error amplifier circuit configured to amplify a difference between a reference voltage and a divided voltage obtained by dividing an output voltage output from the output transistor, and output the amplified difference, thereby controlling a gate of the output transistor;
- and
- a voltage drop circuit connected between the power supply terminal and a drain of the output transistor.
1 more element
Dependencies are inferred from the claim text.