Application programming interface to enable the construction of pipeline parallel programs
AssigneeNVIDIA Corporation
InventorIgnacio LLAMAS
Life of this patent
Estimating the term…
Abstract
An application programming interface (API) provides various software constructs that allow a developer to assemble a processing pipeline having arbitrary structure and complexity. Once assembled, the processing pipeline is configured to include a set of interconnected pipestages. Those pipestages are associated with one or more different CTAs that may execute in parallel with one another on a parallel processing unit. The developer specifies the configuration of the pipestages, including the configuration of the different CTAs across all pipestages, as well as the different processing operations performed by each different CTA.
Claims20
A computer-implemented method for executing a plurality of cooperative thread arrays (CTAs) in parallel with one another, the method comprising:
- causing a first CTA to be launched on a first processing core, wherein the first CTA is associated with a first pipestage that is configured according to first configuration data and included within a processing pipeline;
- causing a second CTA to be launched on a second processing core, wherein the second CTA is associated with a second pipestage that is configured according to second configuration data and included within the processing pipeline;
- and
- causing the first CTA and the second CTA to be executed in parallel, wherein the first CTA executes according to the first configuration data and the second CTA executes according to the second configuration data, and wherein the first configuration data is different than the second configuration data.
A non-transitory computer-readable medium storing program instructions that, when executed by a processing unit, cause the processing unit to execute a plurality of cooperative thread arrays (CTAs) in parallel with one another, by performing the steps of:
- causing a first CTA to be launched on a first processing core, wherein the first CTA is associated with a first pipestage that is configured according to first configuration data and included within a processing pipeline;
- causing a second CTA to be launched on a second processing core, wherein the second CTA is associated with a second pipestage that is configured according to second configuration data and included within the processing pipeline;
- and
- causing the first CTA and the second CTA to be executed in parallel, wherein the first CTA executes according to the first configuration data and the second CTA executes according to the second configuration data, and wherein the first configuration data is different than the second configuration data.
A system for executing a plurality of cooperative thread arrays (CTAs) in parallel with one another, including:
- a processing engine configured to:
- cause a first CTA to be launched on a first processing core, wherein the first CTA is associated with a first pipestage that is configured according to first configuration data and included within a processing pipeline,
- cause a second CTA to be launched on a second processing core, wherein the second CTA is associated with a second pipestage that is configured according to second configuration data and included within the processing pipeline, and
- cause the first CTA and the second CTA to be executed in parallel, wherein the first CTA executes according to the first configuration data and the second CTA executes according to the second configuration data, and wherein the first configuration data is different than the second configuration data.
Dependencies are inferred from the claim text.