Layout modification method and system

A non-transitory, machine readable storage medium encoded with computer program code, such that when the computer program code is executed by a processor, the processor performs a method comprising:

• inspecting a description of a layout of a layer of an integrated circuit (IC) that satisfies a first specification value, the description specifying a plurality of polygons;
• identifying a plurality of first standard cells comprising first devices and having a respective layer matching the plurality of polygons in the description of the layout of the IC;
• identifying timing paths, each connecting a respective two or more of the first standard cells;
• and
• selecting at least one of the identified timing paths such that, if the first devices in the first standard cells of the identified timing paths are replaced by second devices to form a modified layout of a modified IC, the modified IC satisfies a second specification value.

A system comprising:

• one or more non-transitory, machine-readable storage mediums storing a set of standard cell descriptions for making a photomask for fabricating an integrated circuit (IC), and storing a description of a portion of a layout of an IC containing first devices;
• a processor configured to identify portions of the description of the layout which match one or more of the standard cells in the library,
• said processor configured to identify one or more timing paths in the description of the layout connecting standard cells identified by the processor,
• said processor configured for comparing a delay corresponding to each timing path identified by the processor with a performance target, and
• said processor configured to apply a criterion to determine whether to substitute second devices for first devices in the timing paths to meet a second performance target.