Lsi design apparatus and method of designing lsi
AssigneeKabushiki Kaisha Toshiba
InventorsTakeki OSANAI, Makoto Ichida
Life of this patent
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Abstract
According to one embodiment, a LSI design apparatus includes a first logic synthesis portion executing a design of a LSI in a logic gate level, a extraction portion extracting paths from the LSI, a determination portion determining a character of each of the paths, a parameter setting portion setting an upper limit of a transition time of a signal on each of the paths independently based on the character of each of the paths, and a second logic synthesis portion revising the design of the LSI generated in the first logic synthesis portion by optimizing each of the paths so that each of the paths satisfies the upper limit of the transition time of the signal.
Claims20
A LSI design apparatus comprising:
- a first logic synthesis portion executing a design of a LSI in a logic gate level;
- a extraction portion extracting paths from the LSI;
- a determination portion determining a character of each of the paths;
- a parameter setting portion setting an upper limit of a transition time of a signal on each of the paths independently based on the character of each of the paths;
- and
- a second logic synthesis portion revising the design of the LSI generated in the first logic synthesis portion by optimizing each of the paths so that each of the paths satisfies the upper limit of the transition time of the signal.
A method of designing a LSI, the method comprising:
- executing a design of a LSI in a logic gate level by using a first logic synthesis portion;
- extracting paths from the LSI by using a extraction portion;
- determining a character of each of the paths by using a determination portion;
- setting an upper limit of a transition time of a signal on each of the paths independently based on the character of each of the paths by using a parameter setting portion;
- and
- revising the design of the LSI generated in the first logic synthesis portion by optimizing each of the paths so that each of the paths satisfies the upper limit of the transition time of the signal, by using a second logic synthesis portion.
A LSI design apparatus comprising:
- a first logic synthesis portion executing a design of a LSI in a logic gate level;
- a parameter setting portion changing an upper limit of a transition time of a signal on a path extracting from the LSI based on a character of the path;
- and
- a second logic synthesis portion revising the design of the LSI generated in the first logic synthesis portion so that the path satisfies the upper limit of the transition time of the signal.
Dependencies are inferred from the claim text.