Controller to manage nand memories

A storage system to couple to a host processor, the storage system comprising:

• a memory stack including a plurality of raw NAND memory devices, none of the plurality of raw NAND memory devices internally implementing an error correcting code (ECC) algorithm;
• a NAND interface device coupled to the plurality of raw NAND memory devices, the NAND interface being configured to provide power to a single one of the plurality of raw NAND memory devices in the memory stack at a time to reduce power consumption of the storage system;
• and
• a controller coupled to the NAND interface device and external to the plurality of raw NAND memory devices, the controller to export to the host processor a virtualized address space to allow the host to drive the storage system as a single NAND memory device regardless of an actual number of the raw NAND memory devices within the memory stack, the controller further to provide a single virtualized ECC algorithm for each of the plurality of raw NAND memory devices.

A controller to interface with a plurality of raw NAND memory devices included in a memory stack in a storage system, the controller comprising:

• a protocol interface circuit to exchange signals with a host processor;
• an Error Correcting Code (ECC) engine coupled to the protocol interface circuit to implement an ECC algorithm for the plurality of raw NAND memory devices within the memory stack, none of the plurality of raw NAND memory devices internally implementing an error correcting code (ECC) algorithm;
• and
• a NAND interface coupled to the ECC engine to manage the plurality of raw NAND memory devices, the NAND interface being configured to emulate commands issued by the host processor that are not supported by the plurality of raw NAND memory devices, the NAND interface further configured to provide power to a select one of the plurality of raw NAND memory devices at a time to conserve overall power consumption of the storage system.

A method of managing a plurality of raw NAND memory devices in a memory stack that do not internally implement an Error Correcting Code (ECC) algorithm, the method comprising:

• using a protocol interface block of a controller device to exchange signals with a host processor to allow the host processor to communicate with memory stack as a single device regardless of an actual number of raw NAND memory devices within the memory stack;
• implementing a single virtualized ECC algorithm for each of the plurality of raw NAND memory devices by an ECC engine block embedded in the controller device;
• and
• providing power to a single one of the plurality of raw NAND memory devices in the memory stack at a time to reduce power consumption.