Shift Register-Based Layered Low Density Parity Check Decoder

A method of decoding data in a low density parity check layer decoder, comprising:

• generating variable node to check node messages based on check node to variable node messages for a current layer and a previous layer;
• generating intermediate check node messages based on the variable node to check node messages;
• storing the intermediate check node messages in a shift register based memory;
• generating the check node to variable node messages based on the intermediate check node messages from the shift register based memory;
• and
• calculating perceived data values based on the check node to variable node messages.

A storage system comprising:

• a storage medium maintaining a data set;
• a write head operable to magnetically record the data set to the storage medium;
• and
• a low density parity check layer decoder comprising:
• a variable node processor operable to generate variable node to check node messages based on check node to variable node messages;
• and
• a check node processor comprising an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.