Interface to full and reduced pin jtag devices

A substrate comprising:

• A. a full pin device having a full pin interface that includes a test data in lead, a test clock lead, a test mode select lead, and a test data out lead;
• B. a reduced pin device having a reduced pin interface, the reduced pin interface having no more than two leads, of which one is a data input and output lead;
• and
• C. interface circuitry including:
• i. addressable interface circuitry having an interface bus that includes a test data input, a test clock input, a test mode select input, a test data output, and an internal bus that includes a test data output, a test clock output, a test mode select output, a test data input, a full pin select output, and a reduced pin select output;
• ii. full pin interface circuitry having a full pin interface bus coupled to the full pin interface of the full pin device, having an internal bus coupled to the internal bus of the addressable interface circuitry, and having a full pin select input coupled to the full pin select output;
• and
• iii. reduced pin interface circuitry having a reduced pin interface bus coupled to the reduced pin interface of the reduced pin device, having an internal bus coupled to the internal bus of the addressable interface circuitry, and having a reduced pin select input coupled to the reduced pin select output.