Single check memory devices and methods

#Non-volatile memory devices such as flash memory devices are used in many computers and electronic devices to store information (e.g. data). A flash memory device usually has a programming operation to store data, a read operation to retrieve the stored data, and an erase operation to clear data from the memory. These programming, read, and erase operations often involve applying various voltages to different parts of the memory device.

#A conventional non-volatile memory device may go through many programming, read, and erase operations during its life. Thus, improper control of the voltages applied to the device during these operations may lead to inferior device performance, reliability, or both.

#FIG. 1 shows a block diagram of a memory device, according to an embodiment of the invention.

#FIG. 2 shows a partial schematic diagram of a memory device, according to an embodiment of the invention.

#FIG. 3 shows an example of threshold voltage distributions for a memory device, according to an embodiment of the invention.

#In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and logical, electrical changes, etc. may be made.

#FIG. 1 shows a block diagram of a memory device 100 according to an embodiment of the invention. Memory device 100 includes a memory array 102 with memory cells 103 that may be arranged in rows and columns along with access lines 104 and data lines 105. Memory device 100 can use access lines 104 to access memory cells 103 and data lines 105 to transfer information with memory cells 103. Row access 107 and column access circuitry 108 respond to an address register 112 to access memory cells 103 based on row address and column address signals on terminals 110, 111, or both. A data input/output circuit 114 transfers data between memory cells 103 and terminals 110. Terminals 110 and 111 may be external terminals of memory device 100 (e.g., terminals exposed outside a chip or semiconductor package that contains memory device 100).

#A control circuit 116 controls operations of memory device 100 based on signals present on terminals 110 and 111. A device (e.g., a processor or a memory controller) external to memory device 100 may send different commands (e.g., programming commands and read commands) to memory device 100 using different combinations of signals on terminals 110, 111, or both.