Voltage-controllable power-mode-aware clock tree, and synthesis method and operation method thereof

A synthesis method of a voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC), comprising:

• respectively disposing a sub clock tree in at least two function modules of the IC to transmit delayed clocks to different devices in the corresponding function modules;
• disposing at least two PMA buffers to delay a system clock as the delayed clocks, wherein each of the at least two PMA buffers is coupled to the sub clock tree in the corresponding function module to provide the delayed clock;
• and
• disposing a power mode control circuit, wherein the power mode control circuit respectively provides at least two first power information to the at least two function modules to respectively determine power modes of the at least two function modules, and the power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine delay time of the at least two PMA buffers, wherein the at least two first power information is independent to the at least two second power information.

An operation method of a voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC), wherein the PMA clock tree comprises at least two PMA buffers and at least two sub clock trees respectively disposed in at least two function modules of the IC, and the operation method comprises:

• respectively transmitting delayed clocks to different devices in the corresponding function modules by using the at least two sub clock trees;
• respectively delaying a system clock by using the at least two PMA buffers to obtain the delayed clocks, and respectively providing the delayed clocks to the sub clock trees in the corresponding function modules;
• respectively providing at least two first power information to the at least two function modules to respectively determine power modes of the at least two function modules;
• and
• respectively providing at least two second power information to the at least two PMA buffers to respectively determine delay time of the at least two PMA buffers, wherein the at least two first power information is independent to the at least two second power information.