Integrated circuit wake-up control system

An integrated circuit (IC), comprising:

• first and second sets of circuits;
• a high power regulator that provides a first regulated supply voltage to the first and second sets of circuits when the IC is in a high power mode and is switched off when the IC is in a low power mode;
• a low power regulator that provides a second regulated supply voltage to the second set of circuits when the IC is in the low power mode and is switched off when the IC is in the high power mode;
• and
• a switch, connected between the high power regulator and the second set of circuits, for connecting the high power regulator to the second set of circuits when the IC is in the high power mode, and disconnecting the high power regulator from the second set of circuits when the IC is in the low power mode,
• wherein the second set of circuits includes a wake-up control system connected to the high and low power regulators and the switch, and wherein the wake-up control system includes:
• a high frequency clock source for generating a high frequency clock signal and a low frequency clock source for generating a low frequency clock signal;
• a switch state indicator, connected to the switch, for indicating whether the switch is open or closed;
• a wake-up state machine, that enables the high power regulator when the IC transitions from the low power mode to the high power mode and closes the switch to connect the high power regulator to the second set of circuits when the high power regulator reaches a first threshold voltage, and wherein the wake-up state machine operates on the low frequency clock signal when the IC transitions from the low power mode to the high power mode and the switch is open, and operates on the high frequency clock signal when the switch is closed;
• a clock multiplexer having a first input terminal connected to the low frequency clock source for receiving the low frequency clock signal, a second input terminal connected to the high frequency clock source for receiving the high frequency clock signal, a select terminal connected to the switch state indicator for receiving a current state of the switch, and an output terminal connected to the wake-up state machine, wherein the clock multiplexer provides the low frequency clock signal to the wake-up state machine when the switch is open and provides the high frequency clock signal to the wake-up state machine when the switch is closed;
• and
• a wake-up signal generator, connected to the low frequency clock source, for generating a wake-up signal to enable the low frequency clock source when the IC transitions from the low power mode to the high power mode.