Programming interface and method
AssigneeFreescale Semiconductor, Inc.
InventorsArjun Pal Chowdhury, Neha Agarwal, Chandan Gupta, Ankush Sethi
Life of this patent
Estimating the term…
Abstract
A programming interface and method of operating a programming interface use a system clock input, an asynchronous reset input, and an interface control input. The method selectively controls multiplexed coupling of a source register to a destination register and the destination register to a buffer register. The multiplexed coupling of the destination register to the buffer register reduces the possibility of the buffer register being corrupted when an asynchronous reset signal is applied to the programming interface. Problems associated with meta-stable asynchronous crossing paths in asynchronous reset programming systems are therefore alleviated.
Claims20
A programming interface, comprising:
- a system clock input, an interface data bus input, an interface data bus output, an asynchronous reset input and an interface control input;
- a destination register with a destination register clock input coupled to the system clock input, a destination register data input and a destination register data output;
- a buffer register with a buffer register clock input coupled to the system clock input, a buffer register data input and a buffer register data output coupled to the interface data bus output;
- a buffer multiplexer with a buffer multiplexer control input, a buffer multiplexer output coupled to the buffer register data input, a buffer multiplexer first input coupled to the buffer register data output and a buffer multiplexer second input coupled to the destination register data output, wherein the buffer multiplexer couples the buffer multiplexer second input to the buffer multiplexer output when a write signal pulse is applied to the buffer multiplexer control input, otherwise the buffer multiplexer couples the buffer multiplexer first input to the buffer multiplexer output;
- a tertiary multiplexer with a tertiary multiplexer control input, a tertiary multiplexer output, a tertiary multiplexer first input coupled to the destination register data output and a tertiary multiplexer second input coupled to the buffer register data output;
- a destination multiplexer with a destination multiplexer control input coupled to the interface control input, a destination multiplexer output coupled to the destination register data input, a destination multiplexer first input coupled to the tertiary multiplexer output and a destination multiplexer second input coupled to the interface data bus input;
- and
- a pulse delay module with a pulse delay module clock input coupled to the system clock input, a pulse delay module output coupled to the buffer multiplexer control input and a pulse delay module data input coupled to the interface control input,
- wherein in operation when an asynchronous register reset signal is applied to the asynchronous reset input the write signal pulse supplied at the interface control input is blocked from being provided at the pulse delay module output.
A method of controlling a programming interface that includes a system clock input coupled to a destination register and a buffer register with an output coupled to a programmable module, the interface being coupled to a controller that includes a source register coupled to the common clock, the method comprising:
- selecting a multiplexed coupling of an input of the destination register to an output of the destination register;
- selecting a multiplexed coupling of an input of the buffer register to the output of the buffer register;
- detecting a write signal to transfer data from the source register to the destination register;
- modifying the multiplexed coupling of the input of the destination register to couple an output of the source register to the input of the destination register;
- detecting whether an asynchronous register reset signal has reset the contents of the source register;
- modifying the multiplexed coupling of the input of the buffer register to couple an output of the destination register to the input of the buffer register, wherein the coupling of input of the destination register to the output of the buffer register is allowed to occur only after the asynchronous reset signal is released and thereafter at least one clock cycle of a clock signal is applied to the system clock input.
Dependencies are inferred from the claim text.