Unique packed data element identification processors, methods, systems, and instructions

A system comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor operable, in response to a unique packed data element identification instruction that is to indicate a source packed data including a plurality of packed data elements and is to indicate a destination, to store a unique packed data element identification result in the destination, the unique packed data element identification result to indicate which of the plurality of the packed data elements are unique in the source packed data;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect.

An apparatus comprising:

• a first packed data register;
• a second packed data register;
• and
• an execution unit coupled with the first and second packed data registers, the execution unit to receive a two source unique inter-packed data element identification instruction, the instruction to indicate the first packed data register, the second packed data register, and a destination storage location, the first packed data register to have a first source packed data including a first plurality of packed data elements, the second packed data register to have a second source packed data including a second plurality of packed data elements, the execution unit operable, in response to the instruction, to store a unique packed data element identification result in the destination storage location, the unique packed data element identification result to indicate which of the first plurality of the packed data elements of the first source packed data are unique in the second plurality of the packed data elements of the second source packed data.