US 2014/0351565 A1 · SYSTEM AND APPARATUS FOR GROUP FLOATING-POINT INFLATE AND DEFLATE OPERATIONS

Abstract

Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

Claims42

Dependent claims

1-22. (canceled)

A data processing system comprising:

(a) a bus coupling components in the data processing system;
(b) an external memory coupled to the bus;
(c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising:
an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path;
and
an execution unit coupled to the instruction path and the data path and operable to:
decode a single instruction for selectively arranging data, specifying a data selection operand and a first and a second register each having a register width, the single instruction independently specifying the first register and the second register, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width, the data selection operand comprising a plurality of fields each selecting any one of the plurality of data elements and each field having a value not restricted by the other fields included in the data selection operand;
and
provide in parallel the data elements selected by the fields to respective predetermined positions in a catenated result, wherein the predetermined positions are in the same order as the fields of the data selection operand.

10 more elements

A programmable processor comprising:

an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path;
and
an execution unit coupled to the instruction path and the data path and operable to:
decode a single instruction specifying a first register storing a first plurality of data elements, a second register storing a second plurality of data elements, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register;
wherein the single instruction independently specifies the first register and the second register;
wherein each of the first and second registers has a register width, and each of the first and second plurality of data elements has an elemental width smaller than the register width;
wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the first and second pluralities of data elements stored in the first and second pluralities of registers, allowing the index to select any data element from the first and second pluralities of data elements stored in the first and second pluralities of registers;
wherein each index in the index vector has a value not restricted by the other indices in the index vector;
and
provide in parallel data elements from the first and second pluralities of data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register,
wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register.

12 more elements

A data processing system comprising:

(a) a bus coupling components in the data processing system;
(b) an external memory coupled to the bus;
(c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising:
an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path;
and
an execution unit coupled to the instruction path and the data path and operable to:
decode a single instruction specifying a plurality of registers each having a register width, the plurality of registers independently specified by the single instruction and storing a plurality of data elements each having an elemental width smaller than the register width, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register;
wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the plurality of data elements stored in the plurality of registers, allowing the index to select any data element from the plurality of data elements stored in the plurality of registers;
wherein each index in the index vector has a value not restricted by the other indices in the index vector;
and
provide in parallel the data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register.

12 more elements

A data processing system comprising:

(a) a bus coupling components in the data processing system;
(b) an external memory coupled to the bus;
(c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising:
an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path;
and
an execution unit coupled to the instruction path and the data path and operable to:
decode a single instruction specifying a first register storing a first plurality of data elements, a second register storing a second plurality of data elements, an index register storing an index vector comprising a plurality of indices stored in partitioned fields of the index register and a destination register;
wherein the single instruction independently specifies the first register and the second register;
wherein each of the first and second registers has a register width, and each of the first and second plurality of data elements has an elemental width smaller than the register width;
wherein each index in the index vector comprises a sufficient number of bits to represent a range of possible index values, the range of possible index values including a different index value for each of the first and second pluralities of data elements stored in the first and second pluralities of registers, allowing the index to select any data element from the first and second pluralities of data elements stored in the first and second pluralities of registers;
wherein each index in the index vector has a value not restricted by the other indices in the index vector;
and
provide in parallel data elements from the first and second pluralities of data elements selected by the indices to respective predetermined positions in the destination register, wherein the predetermined positions are in the same order as the indices stored in the partitioned fields of the index register,
wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/223,741Filed 24 Mar 2014

Priority

16 Aug 1995

Published

27 Nov 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification29 codes

G06F 9/30014
Arithmetic instructions: with variable precision
G06F 9/30018
To perform operations on data operands: bit or string instructions
G06F 9/30025
To perform operations on data operands: format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
G06F 9/30029
To perform operations on data operands: logical and Boolean instructions, e.g. XOR, NOT

Family

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