Methods for operating and configuring a reconfigurable processor

A computing device comprising:

• a non-transitory computer readable medium storing computer readable code;
• a processor configured to execute the computer readable code so as to be configured as a compiler of computer program instructions for implementation on a reconfigurable processor comprising a plurality of operational cells, each operational cell being connectable to and disconnectable from one or more of the other operational cells via a programmable interconnect, the compiler comprising a routing module configured to perform:
• a routing step in which one or more reconfigurable signal processing paths are determined for performing one or more signal processing operations defined by the computer program instructions, each reconfigurable signal processing path comprising two or more of the operational cells connected via the programmable interconnect, the said signal processing paths being capable of implementation on the said operational cells and the said interconnect of the reconfigurable processor to perform the said one or more signal processing operations;
• and a post-routing step subsequent to the routing step in which an extended signal processing path is determined by extending one of the said signal processing paths such that a critical path of the extended signal processing path is longer than a longest critical path of the reconfigurable signal processing paths determined in the routing step.

A non-transitory computer readable medium storing computer readable code which when executed by a computing device causes the computing device to provide functionality comprising:

• a compiler of computer program instructions for implementation on a reconfigurable processor comprising a plurality of operational cells, each operational cell being connectable to and disconnectable from one or more of the other operational cells via a programmable interconnect, the compiler comprising a routing module configured to perform:
• a routing step in which one or more reconfigurable signal processing paths are determined for performing one or more signal processing operations defined by the computer program instructions, each reconfigurable signal processing path comprising two or more of the operational cells connected via the programmable interconnect, the said signal processing paths being capable of implementation on the said operational cells and the said interconnect of the reconfigurable processor to perform the said one or more signal processing operations;
• and a post-routing step subsequent to the routing step in which an extended signal processing path is determined by extending one of the said signal processing paths such that a critical path of the extended signal processing path is longer than a longest critical path of the reconfigurable signal processing paths determined in the routing step.