Digital signal processor and method for addressing a memory in a digital signal processor
AssigneeMedia Tek Sweden AB
InventorsAnders Nilsson, Eric Tell, Erik Alfredsson
Life of this patent
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Abstract
In a digital signal processor comprising at least one vector execution unit and at least a first memory unit a third unit is arranged to provide addressing data in the form of an address vector to be used for addressing the first memory unit said third unit being connectable to the first memory unit through the on-chip network, in such a way that data provided from the third unit can be used to control the reading from and/or the writing to the first memory unit. This enables fast reading from and writing to a memory unit of data in any desired order.
Claims15
A digital signal processor comprising at least one functional unit, which may be a vector execution unit, a scalar execution unit or an accelerator, and at least a first memory unit arranged to provide data to be operated on by the functional unit, a third unit and an on-chip network connecting the functional unit, the first memory unit and the third unit, said digital signal processor being characterized in that the third unit is arranged to provide addressing data in the form of an address vector to be used for addressing the first memory unit, said third unit being connectable to the first memory unit in such a way that data provided from the third unit can be used to control the reading from and/or the writing to the first memory unit and that the processor further comprises a memory address interface unit arranged to compensate for the latency between the first and the third unit by serving as an intermediate storage of the address items retrieved from the third unit.
A method of addressing a memory in a digital signal processor comprising at least one functional unit, which may be a vector execution unit, a scalar execution unit or an accelerator, and at least a first memory unit arranged to provide data to be operated on by the vector execution unit, and an on-chip network connecting the vector execution unit and the first memory unit, and a third unit arranged to provide addressing data for the first memory unit in the form of an address vector, said method comprising the steps of
- setting the first memory unit to receive addressing data from the third unit,
- providing addressing data from the third unit to the first memory unit,
- reading data from, or writing data to the first memory unit according to the addressing data,
- compensating for the latency between the first and the third unit by means of a memory address interface unit arranged to serve as an intermediate storage between the first and the third unit, for the address items retrieved from the third unit.
Dependencies are inferred from the claim text.