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US 2014/0351554 A1Published application
Linear to physical address translation with support for page attributes
AssigneeIntel Corporation
InventorsOhad Falik, Ben-Zion Friedman, Jacob Doweck, Eliezer Weissmann, James B Crossland
Life of this patent
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Abstract
Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
Claims14
-20. (canceled)
A computing system comprising:
- a modem;
- a random access memory;
- an I/O device;
- a processor comprising:
- a plurality of registers;
- at least one translation look aside buffer, wherein the at least one translation look aside buffer is to include a plurality of entries, wherein at least one entry is to include a physical address and a plurality of attributes associated with the physical address;
- a page miss handler to perform a table walk;
- and
- a physical address return register, wherein the physical address return register is a 64-bit register,
- wherein the processor is to receive an instruction to translate a virtual address to a physical address, wherein the instruction is a kernel level privileged instruction, and
- wherein the instruction is to cause the processor, when in a 64-bit mode, to:
- translate the virtual address to the physical address;
- store the physical address translated from the virtual address in the physical address return register;
- and
- store at least one attribute associated with the physical address translated from the virtual address in the physical address return register.
12 more elements
A computing system comprising:
- a modem;
- a random access memory;
- an I/O device;
- and
- a processor comprising:
- a plurality of registers;
- at least one translation look aside buffer, wherein the at least one translation look aside buffer is to include a plurality of entries, wherein at least one entry is to include a physical address and a plurality of attributes associated with the physical address;
- a page miss handler to perform a table walk;
- and
- a physical address return register, wherein the physical address return register is a 64-bit register,
- wherein the processor is to receive an instruction to translate a virtual address to a physical address, wherein the instruction is a kernel level privileged instruction, and
- wherein the instruction is to cause the processor, when in a 64-bit mode, to:
- start to translate the virtual address to the physical address;
- store an indication that a fault occurred in the physical address return register;
- and
- store a level at which the fault occurred in the physical address return register.
13 more elements
Dependencies are inferred from the claim text.