Dead block predictors for cooperative execution in the last level cache
AssigneeIntel Corporation
InventorsRagavendra Natarajan, Jayesh Guar, Nithiyanandan Bashyam, Mainak Chaudhuri, Sreenivas Subramoney
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Abstract
A cache memory eviction method includes maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is indicative of a number of times a cache block is accessed by a first thread, associating a cache block with one of a plurality of bins based on cache access data values of the cache block, and selecting a cache block to evict from a plurality of cache block candidates based, at least in part, upon the bins with which the cache block candidates are associated.
Claims22
A processor, comprising:
- a plurality of processing cores;
- a cache memory subsystem, comprising:
- a plurality of core caches, each of the core caches corresponding to one of the processing cores;
- a shared cache, common to each of the processing cores;
- trip count (TC) logic to increment a thread-aware trip count for a block recalled from the shared cache to a first core cache;
- use count (UC) logic to increment a UC for a block responsive to each access of the block in the first core cache;
- shared block logic to set a shared block bit for a block accessed by multiple core caches;
- bin logic to maintain live block counts and dead block counts for each bin, wherein:
- a bin corresponds to a (UC, TC) pair;
- a live block count indicates a number of valid, unshared blocks associated with a bin;
- and
- a dead block count indicates a number of blocks evicted from a corresponding bin;
- and
- eviction logic to select a shared cache block to evict, from a plurality of eviction candidates, based on at least one of:
- trip count values, UC values, live bin counts, and dead bin counts.
A cache memory eviction method, comprising:
- maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is indicative of a number of times a cache block is accessed by a first thread;
- and
- associating a cache block with one of a plurality of bins based on cache access data values of the cache block;
- selecting a cache block to evict from a plurality of cache block candidates based, at least in part, upon the bins with which the cache block candidates are associated.
A computer system, comprising:
- a processor including a core region including a plurality of processing cores, each processing core including a core cache, and a shared cache shared among the core caches;
- a memory controller integrated in an uncore region of the processor;
- and
- an I/O hub connected to the processor;
- wherein the processor includes dead block prediction logic to:
- maintain shared block bits indicative of when a block is shared;
- maintain cache access data indicative of a number of times an unshared block is accessed;
- associate unshared blocks with bins based on their cache access data;
- maintain live block counts and dead block counts for each bin;
- and
- select blocks to evict based on the cache access data, the live block counts, and the dead block counts.
Dependencies are inferred from the claim text.