System and method for providing cache-aware lightweight producer consumer queues
AssigneeLSI Corporation
InventorRobert J. Munoz
Life of this patent
Estimating the term…
Abstract
Aspects of the disclosure pertain to a system and method for providing cache-aware lightweight producer consumer queues. The system is a multiprocessor system configured for specifying separate cache attributes for inner (e.g., local) cache and outer (e.g., shared) cache for promoting lower system overhead. Separate cache attributes are specified such that shared variables are cacheable only in a cache level shared by multiple processors.
Claims20
A method of operation of a multiprocessor system, the method comprising:
- determining via a first processor of the system if advancing a first variable of a buffer from a first location in the buffer to a second location in the buffer would make the first variable equal to a second variable, the first variable and the second variable being processor local variables;
- when determining indicates that advancing the first variable from the first location to the second location would not make the first variable equal to the second variable, performing steps of:
- storing requested data to the buffer at a pointer specified by the first variable;
- and
- advancing the first variable to the second location in the buffer.
A non-transitory computer-readable medium having computer-executable instructions for performing a method of operation of a multiprocessor system, the method comprising:
- determining via a first processor of the system if advancing a first variable of a buffer from a first location in the buffer to a second location in the buffer would make the first variable equal to a second variable, the first variable and the second variable being processor local variables;
- when determining indicates that advancing the first variable from the first location to the second location would not make the first variable equal to the second variable, performing steps of:
- storing requested data to the buffer at a pointer specified by the first variable;
- advancing the first variable to the second location in the buffer;
- and
- executing a data memory barrier instruction for allowing prior writes to memory of the system to be detected before a next instruction executes.
A multiprocessor system, comprising:
- a first processor, the first processor including local cache accessible only by the first processor;
- a second processor communicatively coupled with the first processor, the second processor including local cache accessible only by the second processor;
- a memory, the memory being communicatively coupled with the first processor and the second processor;
- a shared cache, the shared cache configured for being accessible by the first processor and the second processor,
- wherein the system is a distributed processing system and is configured for allocating a copy of a single producer single consumer queue and a copy of shared variables to the shared cache, the shared variables being control variables used by the processors to signal each other and being cacheable only in the shared cache.
Dependencies are inferred from the claim text.