Memory device, host device, and sampling clock adjusting method

A sampling clock adjusting method for a host device connected to a memory device including a nonvolatile semiconductor memory unit through signal lines, the host device including a host controller, a sampling clock adjustment unit, and a clock unit configured to generate a clock signal, the method comprising:

• setting, by the sampling clock adjustment unit, an initial value of a phase of a sampling clock signal determining a sampling point at which the host device receives a signal from the memory device on the basis of a phase of the clock signal, wherein the host controller performs control to send a command signal through a command line, receive a response signal through the command line, send and receive a data signal through data lines, and send a clock signal through a clock line, and wherein the memory device sends the signal in synchronization with the clock signal received from the host device;
• sending, by the host device, a tuning command to the memory device through the command line;
• sending, by the memory device upon receiving the tuning command, a first tuning signal and a second tuning signal for adjusting the phase of the sampling clock signal, wherein a pattern of the first tuning signal and a pattern of the second tuning signal are prestored in a memory device side signal pattern storage, and wherein the first tuning signal is sent through a first signal line, the second tuning signal is sent through a second signal line, and a time period during which the first tuning signal is sent and a time period during which the second tuning signal is sent overlap each other;
• receiving, by the host device, the first tuning signal and the second tuning signal;
• and
• comparing, by the host controller, patterns of the first tuning signal and the second tuning signal received with patterns of the first tuning signal and the second tuning signal prestored in a host side signal pattern storage, and adjusting, by the sampling clock adjustment unit, the phase of the sampling clock signal to an optimum sampling point based on a result of the comparison.