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US 2014/0351489 A1Published application
Mechanism for writing into an eeprom on an i2c bus
AssigneeSTMicroelectronics (Rousset) SAS
InventorFrançois Tailliet
Life of this patent
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Abstract
A method for writing data into an EEPROM connected to an I2C bus, wherein the data to be written is transmitted in frames having a size corresponding to the size of a physical half-page of the memory. The programming of a data page in the memory is performed while another page is being received.
Claims20
A method to write data, comprising:
- providing an EEPROM connected to an I2C bus;
- receiving a first frame of data to be written to the EEPROM, the first frame having a size corresponding to a physical half-page of the EEPROM;
- programming the first frame of data into the EEPROM;
- and
- receiving a second frame of data to be written into the EEPROM while the first frame of data is being programmed.
2 more elements
A memory circuit, comprising:
- a matrix of memory cells organized as a plurality of pages, each page having a size of two raised to the power of an integer N (2N);
- a control circuit coupleable to an I2C bus, the control circuit configured to decode frames passed on the I2C bus;
- at least one buffer memory interposed between the control circuit and the matrix, the at least one buffer memory having a size of at least of at least one half page of the plurality of pages, wherein the control circuit is configured to pass to the at least one buffer memory M bits of a full page of data received on the I2C bus, the M bits of the full page of data to be written to the matrix, and wherein the control circuit is further configured to assert an acknowledgement bit on the I2C bus after the M bits of the full page of data to be written to the matrix has been stored in the at least one buffer memory.
An I2C system, comprising:
- an I2C bus;
- a microcontroller coupled to the I2C bus, the microcontroller configured to write data to addressable devices coupled to the I2C bus;
- an EEPROM configured as an addressable device coupled to the I2C bus, the EEPROM including:
- an array of memory cells organized into pages;
- at least one buffer memory coupled to the array;
- and
- a control circuit, the control circuit configured to decode frames passed on the I2C bus, the control circuit configured to assert an acknowledgement bit on the I2C bus after a stop condition signal has been received and after M bits of a page of data to be written to the array have been received on the I2C bus and stored in the at least one buffer memory.
4 more elements
Dependencies are inferred from the claim text.