Back to results
US 2014/0351482 A1Published application
Multi-processor with selectively interconnected memory units
AssigneePact Xpp Technologies AG
InventorMartin Vorbach
Life of this patent
Estimating the term…
Abstract
A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
Claims8
A multi-processor, comprising:
- a plurality of data processing units, each comprising an arithmetic logic unit;
- a plurality of memory units;
- and
- a bus system selectively interconnecting the plurality of data processing units and the plurality of memory units.
1 more element
Dependencies are inferred from the claim text.