Data processing apparatus and method for communicating between a master device and an asychronous slave device via an interface

A method of operating a data processing apparatus comprising a master device operating from a master clock signal, a slave device operating from a slave clock signal asynchronous to said master clock signal, and an interface between said master device and said slave device, the interface providing a communication path for the transfer of packets between the master device and the slave device, each packet comprising a plurality of bits, the method comprising:

• initiating transactions from the master device, each transaction comprising a plurality of transfers including a master transfer to transmit a packet from the master device to the slave device and a slave transfer to transmit a packet from the slave device to the master device;
• employing a slave clock replica generator to generate a slave clock replica used to control timing of transmission of packets by the master device over the interface, and to control timing of reception by the master device of packets sent by the slave device over the interface;
• in response to a predetermined trigger condition, issuing a sync request transfer over said interface from the master device to the slave device, the sync request transfer having a property identifiable by the slave device irrespective of whether the sync request transfer is synchronised with the slave clock signal;
• responsive to detection of said sync request transfer by the slave device, issuing over said interface to the master device a sync response transfer indicative of at least a frequency of the slave clock signal;
• determining within the slave clock replica generator at least the frequency of the slave clock replica from said sync response transfer;
• and
• referencing at least a portion of the packet of selected slave transfers to determine within the slave clock replica generator a phase of the slave clock replica, said at least a portion of the packet containing at least one transition between a first value and a second value different to said first value;
• whereby the determination of the phase of the slave clock replica is decoupled from the determination of the frequency of the slave clock replica.

A data processing apparatus comprising:

• master means for operating from a master clock signal;
• slave means for operating from a slave clock signal asynchronous to said master clock signal;
• interface means between said master means and said slave means, the interface means for providing a communication path for the transfer of packets between the master means and the slave means, each packet comprising a plurality of bits;
• the master means for initiating transactions, each transaction comprising a plurality of transfers including a master transfer to transmit a packet from the master means to the slave means and a slave transfer to transmit a packet from the slave means to the master means;
• the master means including a slave clock replica generator means for generating a slave clock replica used to control timing of transmission of packets by the master means over the interface means, and to control timing of reception by the master means of packets sent by the slave means over the interface means;
• the master means including control means, responsive to a predetermined trigger condition, for causing a sync request transfer to be issued over said interface means from the master means to the slave means, the sync request transfer having a property identifiable by the slave means irrespective of whether the sync request transfer is synchronised with the slave clock signal;
• the slave means, responsive to detection of said sync request transfer, for issuing over said interface means a sync response transfer indicative of at least a frequency of the slave clock signal;
• the slave clock replica generator means for determining at least the frequency of the slave clock replica from said sync response transfer;
• and
• the slave clock replica generator means further for referencing at least a portion of the packet of selected slave transfers to determine a phase of the slave clock replica, said at least a portion of the packet containing at least one transition between a first value and a second value different to said first value;
• whereby the determination of the phase of the slave clock replica is decoupled from the determination of the frequency of the slave clock replica.