Fma unit, in particular for utilization in a model computation unit for purely hardware-based computing of function models
AssigneeRobert Bosch GmbH
InventorsWolfgang FISCHER, Andre GUNTORO
Life of this patent
Estimating the term…
Abstract
An FMA unit, for carrying out an arithmetic operation in a model computation unit of a control unit, is configured to process input of two factors and one summand in the form of floating point values, and provide a computation result of such processing as an output variable in the form of a floating point value. The FMA unit is designed to carry out a multiplication and a subsequent addition, the bit resolutions of the inputs for the factors being lower than the bit resolution of the input for the summand and the bit resolution of the output variable.
Claims12
A floating point multiply and add operation unit for carrying out an arithmetic operation, comprising:
- processing circuitry configured to obtain two factors and a summand as input variables, that each is in a floating point value format, process the input variables, and output, based on the processing, a computation result in a floating point value format;
- wherein:
- the processing includes multiplying the factors and adding (a) a product of the multiplication and (b) the summand;
- and
- a bit resolution of the multiplied factors is lower than a bit resolution of the summand and is lower than a bit resolution of the computation result.
A model computation unit for a control unit, the model computation unit comprising a processor core, the processor core including:
- a logic unit configured to compute an algorithm, the computation being implemented in hardware;
- and
- a floating point multiply and add operation unit that includes processing circuitry configured to obtain two factors and a summand as input variables, that each is in a floating point value format, process the input variables, and output, based on the processing, a computation result in a floating point value format;
- wherein:
- the processing includes multiplying the factors and adding (a) a product of the multiplication and (b) the summand;
- and
- a bit resolution of the multiplied factors is lower than a bit resolution of the summand and is lower than a bit resolution of the computation result.
A control unit, comprising:
- a software-controlled main arithmetic unit;
- and
- a model computation unit, the model computation unit comprising a processor core that includes:
- a logic unit configured to compute an algorithm, the computation being implemented in hardware;
- and
- a floating point multiply and add operation unit that includes processing circuitry configured to obtain two factors and a summand as input variables, that each is in a floating point value format, process the input variables, and output, based on the processing, a computation result in a floating point value format;
- wherein:
- the processing includes multiplying the factors and adding (a) a product of the multiplication and (b) the summand;
- and
- a bit resolution of the multiplied factors is lower than a bit resolution of the summand and is lower than a bit resolution of the computation result.
Dependencies are inferred from the claim text.